A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.
|Title of host publication||-|
|Number of pages||4|
|Publication status||Published - 1 Jan 2005|
|Event||IEEE Conference on Electron Devices and Solid-State Circuits - |
Duration: 1 Jan 2005 → …
|Conference||IEEE Conference on Electron Devices and Solid-State Circuits|
|Period||1/01/05 → …|